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module au(x_int, y_int, x_frac, y_frac, operation, zero, overflow, result_int, result_frac);
parameter WIDTH_1 = 4, WIDTH_2 = 4;
input [WIDTH_1-1:0] x_int, y_int;
input [WIDTH_2-1:0] x_frac, y_frac;
input operation;
output zero, overflow;
output [WIDTH_1-1:0] result_int;
output [WIDTH_2-1:0] result_frac;
reg z, over;
reg [2*(WIDTH_1)-1:0] r_i;
reg [2*(WIDTH_2)-1:0] r_f;
reg [2*(WIDTH_1+WIDTH_2)-1:0] r_intr;
always @* begin
r_i = 0;
r_f = 0;
if (operation == 1'b0) begin
r_i = x_int + y_int;
r_f = x_frac + y_frac;
if (r_f[WIDTH_2] == 1'b1) r_i += 1;
if (r_i[WIDTH_1] == 1'b1) over = 1'b1;
else over = 1'b0;
end
else begin
r_intr = {x_int, x_frac} * {y_int, y_frac};
r_i[WIDTH_1-1:0] = r_intr[2*WIDTH_2+WIDTH_1-1:2*WIDTH_2];
r_f[WIDTH_2-1:0] = r_intr[2*WIDTH_2-1:WIDTH_2];
if (r_intr[2*(WIDTH_2+WIDTH_1)-1:2*WIDTH_2+WIDTH_1] != 0/* || r_intr[WIDTH_2-1:0] != 0*/)
over = 1'b1;
else
over = 1'b0;
end
if (r_i[WIDTH_1-1:0] == 0 && r_f[WIDTH_2-1:0] == 0) z = 1;
else z = 0;
// z = (r_i == 0 && r_f == 0);
end
assign result_int = r_i[WIDTH_1-1:0];
assign result_frac = r_f[WIDTH_2-1:0];
assign zero = z;
assign overflow = over;
endmodule
/*
module test;
reg [3:0] a, b;
reg [3:0] _a, _b;
reg switch;
wire [3:0] r;
wire [3:0] _r;
wire zero, overflow;
au summer(a, b, _a, _b, switch, zero, overflow, r, _r);
initial begin;
a = 0;
_a = 4'b1100;
b = 0;
_b = 4'b1100;
switch = 1'b0;
#1;
$display("%d.%b %s %d.%b = %d.%b (overflow: %b, zero: %b)",
a, _a, (switch == 1'b0 ? "+" : "*"), b, _b, r, _r, overflow, zero);
end
endmodule
*/
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