module max_argmax(data_in, data_max, argmax);
	parameter WIDTH=8, SIZE=2;
	input [WIDTH*(1<<SIZE)-1:0] data_in;
	output [WIDTH-1:0] data_max;
	output [SIZE-1:0] argmax;
	if (SIZE == 1) begin
		wire [WIDTH-1:0]
			a1 = data_in[WIDTH*2-1:WIDTH],
			a2 = data_in[WIDTH-1:0];
		assign data_max = a1 > a2 ? a1   : a2;
		assign argmax   = a1 > a2 ? 1'b0 : 1'b1;
	end else begin
		wire [WIDTH*(1<<(SIZE-1))-1:0]
			w1 = data_in[WIDTH*(1<<SIZE)-1:WIDTH*(1<<(SIZE-1))],
			w2 = data_in[WIDTH*(1<<(SIZE-1))-1:0];
		wire [WIDTH-1:0] a1, a2;
		wire [SIZE-2:0] i1, i2;
		max_argmax#(WIDTH, SIZE-1) m1(w1, a1, i1);
		max_argmax#(WIDTH, SIZE-1) m2(w2, a2, i2);
		assign data_max         = a1 > a2 ? a1   : a2;
		assign argmax[SIZE-2:0] = a1 > a2 ? i1   : i2;
		assign argmax[SIZE-1]   = a1 > a2 ? 1'b0 : 1'b1;
	end
endmodule

/*
module test;
	reg [63:0]vals;
	wire [7:0]out;
	wire [2:0]idx;
	max_argmax#(8, 3) adder(vals, out, idx);
	initial begin
		$monitor("%d, %b", out, idx);
		vals[63:56] = 25;
		vals[55:48] = 24;
		vals[47:40] = 25;
		vals[39:32] = 13;
		vals[31:24] = 25;
		vals[23:16] = 121;
		vals[15:8] = 2;
		vals[7:0] = 200;
		#1;
	end
endmodule
*/