module tree_adder(data_in, data_out);
	parameter WIDTH=8, SIZE=4;
	input wire [WIDTH*SIZE-1:0] data_in;
	output wire [WIDTH-1:0] data_out;
	if (SIZE == 2) begin
		assign data_out = data_in[WIDTH-1:0] + data_in[2 * WIDTH-1:WIDTH];
	end else begin
		wire [WIDTH-1:0]intmd[0:1];
		tree_adder#(WIDTH, SIZE/2) m1(data_in[SIZE/2*WIDTH-1:0], intmd[0]);
		tree_adder#(WIDTH, SIZE/2) m2(data_in[SIZE*WIDTH-1:SIZE/2*WIDTH], intmd[1]);
		assign data_out = intmd[0] + intmd[1];
	end
endmodule

/*
module test;
	reg [63:0]vals;
	wire [7:0] out;
	tree_adder#(8, 8) adder(vals, out);
	initial begin
		$monitor(out);
		vals[7:0] = 1;
		vals[15:8] = 2;
		vals[23:16] = 1;
		vals[31:24] = 2;
		vals[39:32] = 1;
		vals[47:40] = 1;
		vals[55:48] = 1;
		vals[63:56] = 1;
		#1;
	end
endmodule
*/