module ram(data_in, address, clock, write_enable, data_out);
	parameter DATA_WIDTH = 8;
	parameter ADDR_WIDTH = 4;
	input [DATA_WIDTH-1:0] data_in;
	input [ADDR_WIDTH-1:0] address;
	input clock, write_enable;
	output [DATA_WIDTH-1:0] data_out;
	reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];
	always @(posedge clock) begin
		if (write_enable) mem[address] <= data_in;
	end
	assign data_out = mem[address];
endmodule

/*
module test;
	reg [7:0] in;
	reg [3:0] addr;
	reg clock, ddr;
	wire [7:0] out;
	ram r(in, addr, clock, ddr, out);
	
	always #1 clock = ~clock;

	initial begin
		$monitor(out);
		clock = 0;
		addr = 'hA;
		in = 'h69;
		ddr = 1;
		#10 ddr = 0;
		addr = 'hB;
		in = 'hFF;
		#10 ddr = 1;
		#10 ddr=0;
		addr = 'hC;
		in = 'h01;
		#10 ddr=1;
		#10 ddr=0;
		$display("0x9 to 0xD test");
		#10 addr = 'h9;
		#10 addr = 'hA;
		#10 addr = 'hB;
		#10 addr = 'hC;
		#10 addr = 'hD;
	end;
endmodule
*/