module mux64_4_2(y0, y1, y2, y3, x, z);
	input wire [63:0] y0, y1, y2, y3;
	input wire [1:0] x;
	output wire [63:0] z;
	wire [63:0] mx0, mx1, mx2, mx3[63:0] ;
	genvar i;
	generate for(i = 0; i < 64; i = i + 1) 
		begin: gen
			and(mx0[i], y0[i], ~x[0], ~x[1]);
			and(mx1[i], y1[i], ~x[0], x[1]);
			and(mx2[i], y2[i], x[0], ~x[1]);
			and(mx3[i], y3[i], x[0], x[1]);
			or(z[i], mx0[i], mx1[i], mx2[i], mx3[i]);
		end;
	endgenerate;
endmodule;

/*
module test;
	reg [63:0] a1, a2, a3, a4;
	reg [2:0] muxselect;
	wire [63:0] out;
	mux64_4_2 mux(a1, a2, a3, a4, muxselect[1:0], out);
	initial begin;
		a1 = 69;
		a2 = 420;
		a3 = 727;
		a4 = 1488;
		for (muxselect = 2'b00; muxselect <= 2'b11; muxselect += 1) begin
			#10;
			$display("current thingy: %d", out);
		end;
	end;
endmodule;
*/