From 11508800cfaefc1c25a793760bf10d3fd997af80 Mon Sep 17 00:00:00 2001
From: justanothercatgirl <sotov@twistea.su>
Date: Wed, 14 May 2025 19:16:38 +0300
Subject: Initial and probably final commit

---
 1-e.v | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 1-e.v

(limited to '1-e.v')

diff --git a/1-e.v b/1-e.v
new file mode 100644
index 0000000..b30b9ae
--- /dev/null
+++ b/1-e.v
@@ -0,0 +1,66 @@
+module flipflop(in, clock, reset, out);
+	parameter WIDTH = 8;
+	input [WIDTH-1:0] in;
+	input clock, reset;
+	output [WIDTH-1:0] out;
+	reg [WIDTH-1:0] mem1;
+	
+	/* Вот этот вариант не принял
+	always @(posedge clock) mem1 <= in;
+	always @(posedge reset) mem1 <= 0; */
+	// А вот этот принял
+	always @(posedge clock or posedge reset) begin 
+		if (reset) mem1 <= 0;
+		else mem1 <= in;
+	end
+	// в чём разница ? Я думал, это эквивалентно
+	assign out = mem1;
+endmodule
+
+/*
+module shift_register(data_in, clock, reset, data_out);
+	parameter WIDTH = 8, LENGTH = 4;
+	input [WIDTH-1:0] data_in;
+	input clock, reset;
+	output [WIDTH-1:0] data_out;
+	wire [WIDTH-1:0] inter[0:LENGTH];
+	generate
+		genvar i;
+		for (i = 0; i < LENGTH; i=i+1)
+			flipflop#(WIDTH) f(inter[i], clock, reset, inter[i+1]);
+	endgenerate
+	assign inter[0] = data_in;
+	assign data_out = inter[LENGTH];
+endmodule
+
+module test;
+	reg clock;
+	reg reset;
+	reg [7:0]in;
+	wire [7:0]out;
+	shift_register#(8, 4) sr(in, clock, reset, out);
+	// always #5 clock = ~clock;
+	initial begin
+		$monitor("%d | %d | %b | %b", in, out, clock, reset);
+		clock = 0;
+		reset = 0;
+		#1 reset = 1; #1 clock = 1; #1 clock = 0;
+		reset = 0; #1 clock = 1; #1 clock = 0; 
+		in = 69; #1 clock = 1; #1 clock = 0; 
+		in = 42; #1 clock = 1; #1 clock = 0; 
+		in = 70; #1 clock = 1; #1 clock = 0;
+		in = 111; #1 clock = 1; #1 clock = 0; #1 clock = 1; #1 clock = 0; #1 clock = 1; #1 clock = 1; #1 clock = 0; #1 clock = 1; #1 clock = 0; #1 clock = 1; 
+		reset = 1; #1 clock = 0; #1 clock = 1; 
+		reset = 0; in = 1; #1 clock = 1; #1 clock = 0; 
+		in = 2; #1clock = 1; #1 clock = 0; 
+		in = 3;#1 clock = 1; #1 clock = 0; 
+		in = 4;#1 clock = 1; #1 clock = 0; 
+		in = 5;#1 clock = 1; #1 clock = 0;
+		in = 6; #1 clock = 1; #1 clock = 0;#1 clock = 1; 
+		#1 clock = 0; #1 clock = 1; #1 clock = 0; 
+		#1 clock = 1; #1 clock = 0; #1 clock = 1; 
+		#1 clock = 0; #1 clock = 1; #1 clock = 0;
+	end;
+endmodule;
+*/
+
-- 
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